GaO<i>x</i> interlayer-originated hole traps in SiO2/<i>p</i>-GaN MOS structures and their suppression by low-temperature gate dielectric deposition

Abstract

In this study, we investigated the impact of SiO2 deposition temperature during plasma-enhanced chemical vapor deposition on the generation of fast hole traps, which cause surface potential pinning, in p-type GaN MOS structures. The thickness of a gallium oxide (GaOx) layer at the SiO2/GaN interface was estimated and correlated with the hole trap generation. The 200 °C-deposited SiO2/GaN MOS structures exhibited a smaller amount of fast hole traps and a thinner GaOx interlayer than the 400 °C-deposited samples. In the 200 °C-deposited samples, annealing at a temperature below 600 °C did not lead to an increase in the fast hole trap and GaOx layer thickness, while the amount of fast traps significantly increased just after 800 °C-annealing in O2 ambient, accompanied by the growth of the GaOx interlayer. These findings suggest that the major origin of fast hole traps in SiO2/GaN MOS structures is a thermally induced defect existing inside a GaOx interlayer and that the low-temperature SiO2 deposition is effective in reducing the fast traps.