Three-layer work-function gate for suppressing floating-body effects on vertical-channel DRAM access transistors

Abstract

In vertical-channel transistors used as access transistors in high-density dynamic random-access memory, the body becomes electrically floating, leading to a floating-body effect (FBE) that degrades data retention. Most previous studies have focused on reducing gate-induced drain leakage (GIDL) at the storage node junction to improve “1” state retention, while leaving the “0” state retention unaddressed. This work introduces a three-layer work function (WF) gate structure that symmetrically suppresses the FBE for both states. Low-WF layers are positioned at both ends of the channel to symmetrically suppress GIDL, whereas a high-WF layer in the center maintains channel depletion and thereby prevent retention degradation. Mixed-mode TCAD simulations of single-, dual-, and three-layer WF gates under both dynamic and static retention conditions demonstrate that the proposed design effectively suppresses the FBE in both the “1” and “0” states.