Sliding-engineered multiple conductive states in van der Waals VSe2 devices

S Sichun Zhao (Key Laboratory of Material Physics, Ministry of Education, School of Physics, Zhengzhou University 1 , Zhengzhou 450001,) S Shiqi Liu C Chao Feng (Instrumental Analysis Center (IAC) of Xi’an Jiaotong University, Xi’an Jiaotong University) G Gejing Wang (Key Laboratory of Material Physics, Ministry of Education, School of Physics, Zhengzhou University 1 , Zhengzhou 450001,) C Chao Mao J Jinbo Yang (Institute of Condensed Matter and Material Physics, School of Physics) J Jie Yang

Abstract

Multiferroic (MFE) systems with rich tunability encompassing multiple degrees of freedom like spin and dipole are competitive candidates for nonvolatile memory applications. The development of two-dimensional (2D) MFE configurations could further enhance this technology, facilitating the advancement of next-generation microcontroller units. However, most reported 2D multiferroics rely on spatially separated ferromagnetic and ferroelectric layers, which introduce interfacial complexities and limit device scalability. Here, we design a van der Waals multiferroic tunneling junction using antiferromagnetic VSe2 as a unified magnetic and ferroelectric layer, with 2D metallic TaS2 and Au (intercalated by monolayer graphene, Gr) serving as the right and left electrodes, respectively. Through ab initio quantum transport simulations, we systematically investigate its electronic transport properties. Our results reveal that the device exhibits four switchable ferroelectric conductance states, which can be modulated via interlayer sliding. When the magnetization alignment of trilayer VSe2 is additionally controlled, the number of distinguishable conductance states increases to 12. The conductance difference is quantified by tunneling magnetoresistance and tunneling electroresistance, which can maximally increase to 8000% and 4000%, respectively, under optimized bias voltages. Our research expands the application of 2D antiferromagnetic materials and provides a viable strategy for designing high-performance, multi-state memory devices.

Article Details

Volume / Issue Vol. 127, Issue 12
Published September 22, 2025
ISSN 0003-6951
Publisher American Institute of Physics

Journal Info

Applied Physics Letters

American Institute of Physics

ISSN: 0003-6951 Physical Sciences

Authors (7)

S

Sichun Zhao

Key Laboratory of Material Physics, Ministry of Education, School of Physics, Zhengzhou University 1 , Zhengzhou 450001,

S

Shiqi Liu

C

Chao Feng

Instrumental Analysis Center (IAC) of Xi’an Jiaotong University, Xi’an Jiaotong University

G

Gejing Wang

Key Laboratory of Material Physics, Ministry of Education, School of Physics, Zhengzhou University 1 , Zhengzhou 450001,

C

Chao Mao

J

Jinbo Yang

Institute of Condensed Matter and Material Physics, School of Physics

J

Jie Yang