Punch-through breakdown in high-voltage GaN superjunction HEMT

Abstract

GaN superjunction (SJ) high-electron mobility transistors (HEMTs) have recently emerged as a promising platform for multi-kilovolt power electronics due to their superior electric field management. However, this work reveals that the early channel depletion inherent to the SJ structure introduces a distinct risk of punch-through breakdown, a phenomenon typically observed in short-channel devices but previously seldom reported in high-voltage GaN devices. We report that the fabricated SJ HEMTs capable of a 4.2 kV destructive breakdown at a gate bias of −3 V exhibit a premature leakage surge at only 700 V under zero gate bias. Unlike avalanche breakdown, this punch-through mechanism triggers an uncontrolled current surge and a loss of blocking integrity well below the material's limit. Combined experimental analysis and physics-based simulations identify the mechanism as an electrostatic interplay where SJ depletion magnifies drain-induced barrier lowering. We demonstrate that increasing the gate length from 1.5 to 3.5 μm restores the channel potential barrier and fully suppresses punch-through, enabling 4.2 kV blocking at zero gate bias. Furthermore, the breakdown is found to be sensitive to the SJ region length, as well as surface trap states that modulate the depletion of the access region. These findings provide critical design rules for robust high-voltage GaN superjunction power devices.