Programming optimization for alleviating relaxation effect in RRAM high-resistance state

Abstract

Resistive random access memory (RRAM) is considered a highly promising alternative for brain-inspired computing and next-generation memory technologies. However, the conductance states relaxation effect substantially narrows the operational window, thereby exacerbating the occurrence of data storage errors. This study investigates the relaxation characteristics of the high-resistance state collected from a 2 Kb RRAM array which was fabricated in 28 nm commercial foundry. Three distinct drift behaviors of the RRAM resistance states were observed: (1) transient conductance drift, (2) stair-stepping conductance drift, and (3) reversible conductance drift. A programming strategy based on electron release was proposed to identify unstable devices efficiently. The amplitude and width modulation of the release pulse reveals that amplitude modulation has a more significant effect due to a certain barrier height for trapped electrons to be released. A physical model based on the trap-assisted tunneling mechanism is proposed to fit the cumulative distribution function of unstable bits under different pulse amplitudes and widths. Compared to existing long pulse and delay verify programming strategies, the release verify method significantly reduces the impact of RRAM relaxation while maintaining programming efficiency.