Negative bias threshold voltage instability and gate reliability in GaN tri-gate HEMTs with ferroelectric charge-trap gate stack

Abstract

This study demonstrates trap-induced threshold voltage (VTH) instability in hybrid ferroelectric charge-trap tri-gate high-electron-mobility transistors under temperature and negative bias stress. By applying a moderate negative gate bias (−5 V) over a temperature range of 25–150 °C, we analyze the charge-trapping/detrapping dynamics at the Fin sidewall and dielectric interfaces. Activation energy (Ea) of 0.74 eV confirms the temperature-dependent nature of the trapping mechanisms. Furthermore, partial VTH recovery after stress removal highlights the presence of deep-level sidewall traps with a slow detrapping process. Additionally, by extrapolating time-dependent gate dielectric breakdown (TDDB) data across high-temperature stress conditions, the device demonstrates a 10-year lifetime at 150 °C under an operating voltage of approximately 8.22 V. Furthermore, the extracted Ea ranging from 0.59 to 0.63 eV confirms the presence of deep-level traps within the AlGaN barrier layer, which contributes to the electron trapping during degradation, leading to the point-level defect generation, ultimately driving TDDB.