Negative bias temperature stress-induced threshold voltage instability and mobility degradation in SiC PMOS devices

Abstract

This study reveals a fundamental difference in the degradation mechanisms of 4H-SiC PMOS and NMOS devices under negative bias temperature stress. While NMOS devices exhibit substantial electron mobility degradation exceeding 8% under stress at 300 °C and −40 V for 1000 s, PMOS devices demonstrate remarkable stability, with hole mobility degradation limited to less than 2.5%, despite experiencing significantly higher hole injection into the gate oxide. By applying Matthiessen's rule to decompose mobility components and fitting scattering parameters as functions of effective electric field and temperature (up to 300 °C), we quantitatively pinpoint the dominant degradation mechanisms. For PMOS, phonon scattering prevails under high fields and temperatures, intrinsically limiting mobility via lattice vibrations and rendering it resilient to stress-induced defects. In stark contrast, NMOS degradation stems primarily from a stress-induced enhancement of Coulomb scattering, correlated with the generation of new interface traps. This experimental and decomposition approach quantifies the scattering-specific contributions to degradation, demonstrating that the dominance of phonon scattering preserves PMOS mobility integrity despite significant stress. The methodology offers a framework for reliability-aware design optimization in SiC metal–oxide–semiconductor technology.