Low power and high-speed quadrate node upset tolerant latch design using CNTFET
S
Shaik Asiya
S
Satheesh Kumar S
Article Details
Journal
Scientific Reports
Volume / Issue
Vol. 15, Issue 1
Published
December 22, 2025
ISSN
2045-2322
Publisher
Nature Portfolio
Authors (2)
S
Shaik Asiya
S
Satheesh Kumar S
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