Investigation of channel material purity in fully depleted silicon-on-insulator transistors designed for qubit applications

Abstract

Silicon holds significant potential as a material for future quantum processors. Transistors built in silicon-on-insulator technology and functioning as silicon qubit devices can be fabricated using industry-standard processes, allowing for easy integration with classical control hardware. However, achieving precise management of carrier transfer within the transistor channel is essential, requiring the elimination of electrically active defects that could act as recombination centers. Optimizing such a device demands a detailed characterization of the channel to assess the material purity. This study examines the presence of defects in the channel of fully depleted silicon-on-insulator transistors designed for qubit applications. Source and drain electrodes were connected together and voltage pulses were applied to the gate contact to perform capacitance deep level transient spectroscopy (DLTS) measurements. Electrical simulations conducted using Sentaurus device simulator were used to figure out the extension of the depleted region in the channel. By adjusting the gate voltages, we were able to probe the channel and localize the electrically active defects responsible for DLTS signals. Three dominant hole traps were detected at, respectively, 0.54, 0.57, and 0.65 eV above the valence band edge in the source/drain regions and were associated with bulk and Si/SiO2 interface defects. Their origin is likely related to the damage produced during the formation of p-doping by implantation. This study highlights not only the high quality of the channel material below the gate stack but also the need to keep the source and drain regions far from the gate edges to improve the qubit stability.