Interface-engineered top-gate indium-tin-oxide thin-film transistors with 2-nm channels

Abstract

The fabrication of top-gate (TG) field-effect transistor structure in amorphous oxide semiconductor systems remains challenging due to interfacial degradation associated with oxygen-deficient states at the gate insulator (GI)/channel interface induced during GI deposition. In this work, we demonstrate back-end-of-line-compatible, ultra-thin (2 nm) indium-tin-oxide (ITO) top-gate thin-film transistors (TFTs) enabled by an interface-engineered process that integrates channel surface treatment with stacked GI architecture. A bilayer Al2O3 GI grown with stacked atomic layer deposition (ALD) structure, consisting of thermal-mode ALD (T-ALD) and plasma-enhanced ALD (PE-ALD), is adopted to enhance gate controllability and suppress interfacial degradation. Additionally, an O2-plasma surface treatment on the channel is applied to further improve the channel–GI interface quality. The resulting devices exhibit an on/off current ratio of 108 (VDS = 1 V), a positive threshold voltage of 0.7 V, a subthreshold swing of 89 mV/decade, and a near-hysteresis-free threshold-voltage shift of only 17 mV. These results confirm that the proposed interface-engineering strategy effectively mitigates TG-process-induced degradation and enables high-performance ITO TG TFTs suitable for oxide-semiconductor-based monolithic 3D integrated circuits.