Improving thermal boundary conductance for wafer-scale buffer-free GaN-on-SiC via ion-cutting and controllable annealing

Abstract

Thermal management remains a critical challenge for high-power gallium nitride (GaN) devices, particularly under extreme power densities, primarily due to the low thermal boundary conductance (TBC) limitations. To overcome this, we present an innovative hetero-integration strategy that enables wafer-scale transfer and recycle of 2-in. GaN via the ion-cutting technique, combined with direct buffer-free bonding to a high-thermal-conductivity silicon carbide (SiC) substrate using surface-activated bonding. While this process facilitates wafer-scale transfer and direct bonding, it inherently introduces lattice damage and an amorphous interlayer. Comparison of different annealing protocols reveals that a controllable rapid thermal annealing (RTA) process is superior for repairing the lattice damage inherent to the ion-cutting technique and promoting interfacial atomic reconstruction, which can significantly improve the phonon transport efficiency. Transient thermoreflectance measurements reveal an average 2.6-fold enhancement in the TBC, with a peak value of 3.1-fold improvement, of the RTA-treated 2-in. GaN-on-SiC heterostructure. These findings present a scalable and practical pathway to alleviating thermal limitations in high-power GaN devices through advanced integration techniques, supporting the development of reliable next-generation high-power electronics.