Impedance-engineered Josephson parametric amplifier with single-step lithography

Abstract

We present an experimental demonstration of an impedance-engineered Josephson parametric amplifier (IEJPA) fabricated in a single-step lithography process. Impedance-engineering is implemented using a lumped-element series LC circuit. We use a simpler lithography process where the entire device—impedance transformer and Josephson parametric amplifier (JPA)—is patterned in a single electron beam lithography step, followed by a double-angle Dolan-bridge technique for Al–AlOx–Al deposition. We observe amplification with 18 dB gain over a wide 400 MHz bandwidth centered around 5.3 GHz with added noise approaching the quantum limit, and a saturation power of −114 dBm. To accurately explain our experimental results, we extend existing theories for IEJPAs to incorporate the full sine nonlinearity of both the JPA and the transformer. Our work provides a route to simpler realization of broadband JPAs and a theoretical foundation for a regime of JPA operation that has been less explored in literature.