Impact of high-temperature annealing on oxide semiconductor self-aligned top-gate thin-film transistors with 1 <i>μ</i> m channel length

Abstract

Organic light-emitting diodes on silicon have emerged as a key technology for ultrahigh-resolution near-to-eye (NTE) displays by offering fast response, wide color gamut, and complementary metal–oxide–semiconductor-compatible processing for &amp;gt;2000 pixels per inch (PPI). However, despite achieving high PPI levels, existing NTE displays suffer from limited battery life and prohibitive costs. While oxide semiconductor thin-film transistors (TFTs) are promising alternatives, most studies have focused on low thermal budgets for glass substrates and relatively long channel lengths. Therefore, we experimentally investigated the impact of high annealing temperatures on 1 μm short-channel InSnZnO (ITZO) self-aligned top-gate (SATG) TFTs. A high field-effect mobility of 14.5 cm2/V s is achieved at 450 °C, while a minimum drain-induced barrier lowering of 34.9 mV/V was observed at 850 °C. Thin-film analyses and contact resistance measurements revealed the underlying reasons for the stable operation of high-temperature-annealed ITZO SATG TFTs with 1 μm channel lengths.