Impact of high-pressure annealing on characteristics of InGaAs/InAlAs metamorphic high-electron mobility transistors

S Songyi Han (Department of Electrical and Computer Engineering, Inha University 1 , Incheon,) W Woosub Byun (Department of Electrical and Computer Engineering, Inha University 1 , Incheon,) Y Yeonbin Kang (Department of Electrical and Computer Engineering, Inha University 1 , Incheon,) T Tae-Hyun Kil (School of Semiconductor Engineering, Chungbuk National University 2 , Cheongju,) J Jun-Young Park H Hyunchul Jang (Device Technology Division, Korea Advanced Nano Fab Center (KANC) 3 , Suwon,) D Deoksoo Park (Device Technology Division, Korea Advanced Nano Fab Center (KANC) 3 , Suwon,) Y Yumin Koh (Device Technology Division, Korea Advanced Nano Fab Center (KANC) 3 , Suwon,) J Jae-Phil Shim (Device Technology Division, Korea Advanced Nano Fab Center (KANC) 3 , Suwon,) D Dae-Myeong Geum (Optical Communication Components Research Section, Electronics and Telecommunications Research Institute (ETRI) 1 , Daejeon 34129,)

Abstract

High-pressure annealing (HPA) has emerged as a promising post-fabrication technique for enhancing carrier transport and reliability in semiconductor devices, yet its application to heterojunction-based III–V transistors remains limited. In this study, we explore the implementation of HPA in InGaAs/InAlAs metamorphic high-electron-mobility transistors to understand ambient-dependent effects in heterostructure interfaces. Representative annealing ambients, such as high-pressure nitrogen (HPNA) and deuterium (HPDA), were selected to assess the impact of ambient species on electrical performance. Through comprehensive characterization, including I–V and pulsed measurements and transmission-line method analysis, we systematically examined how HPA conditions influence trap behavior, channel resistance (Rch), and frequency response. HPNA can lead to reproducible improvements in DC performance, with a 6.20% increase in on-state current and a 5.76% enhancement in transconductance, alongside a 17.8% reduction in channel resistance, while maintaining a stable subthreshold swing. In contrast, HPDA-treated devices exhibited increased Rch and enhanced trap-related transient responses, offering insights into trap generation mechanisms in complex III–V interfaces. These results provide a valuable reference for the design of ambient-controlled annealing strategies and highlight the importance of tailoring HPA processes for the reliable integration of heterojunction-based transistors.

Article Details

Volume / Issue Vol. 128, Issue 3
Published January 19, 2026
ISSN 0003-6951
Publisher American Institute of Physics

Journal Info

Applied Physics Letters

American Institute of Physics

ISSN: 0003-6951 Physical Sciences

Authors (10)

S

Songyi Han

Department of Electrical and Computer Engineering, Inha University 1 , Incheon,

W

Woosub Byun

Department of Electrical and Computer Engineering, Inha University 1 , Incheon,

Y

Yeonbin Kang

Department of Electrical and Computer Engineering, Inha University 1 , Incheon,

T

Tae-Hyun Kil

School of Semiconductor Engineering, Chungbuk National University 2 , Cheongju,

J

Jun-Young Park

H

Hyunchul Jang

Device Technology Division, Korea Advanced Nano Fab Center (KANC) 3 , Suwon,

D

Deoksoo Park

Device Technology Division, Korea Advanced Nano Fab Center (KANC) 3 , Suwon,

Y

Yumin Koh

Device Technology Division, Korea Advanced Nano Fab Center (KANC) 3 , Suwon,

J

Jae-Phil Shim

Device Technology Division, Korea Advanced Nano Fab Center (KANC) 3 , Suwon,

D

Dae-Myeong Geum

Optical Communication Components Research Section, Electronics and Telecommunications Research Institute (ETRI) 1 , Daejeon 34129,