Hole trapping and emission behavior near the valence band edge at an AlSiO/ <i>p</i> -type GaN interface revealed by repeated temperature-dependent <i>C</i> – <i>V</i> measurements

Abstract

Bias instability associated with traps near the valence band edge at gate dielectric/p-type GaN interfaces poses a serious reliability concern for GaN metal–oxide–semiconductor field-effect transistors although origins of hole traps are still unclear. This study demonstrates an isolation of trap components with interface states and near-interface traps (NITs) at an AlSiO/p-type GaN interface by analyzing the hole emission process as a function of temperature and sweep time. The gate dielectric was a 40 nm-thick AlSiO film deposited by plasma-enhanced atomic layer deposition at 250 °C and annealed at 400 °C in nitrogen gas. The capacitance–voltage (C–V) characteristics exhibited a significant plateau and no hole accumulation in the valence band of GaN, indicating a high density of interface traps at approximately 0.8 eV above the valence band maximum of GaN. After the first reverse C–V sweep, the subsequent forward sweep showed a large negative shift (hysteresis) that largely persisted in the following reverse sweeps. At elevated temperatures and with slower sweep rates, the shift was partially reduced (recovered); however, a residual shift remained. An Arrhenius analysis of the recovered component yielded an activation energy of approximately 0.8 eV, which was consistent with the Fermi-level pinning position, suggesting that the thermally recovered component is governed by hole emission from interface states. In contrast, the persistent residual shift suggested a negligibly emitting component, i.e., NITs. We, thus, isolated the contribution of interface states from NITs in the hole emission process.