Experimental and modeled analysis of source-line loading effects in NOR flash compute-in-memory arrays

Abstract

We investigate the fundamental electrical mechanisms driving non-ideal current behavior in NOR flash-based compute-in-memory (CIM) arrays. Measurements from an industrial 45 nm NOR flash process identify loading effects as the dominant degradation source. Unlike the conventional view that attributes loading primarily to bit-line voltage drop, we show it is more strongly governed by source-line voltage elevation from cumulative column current, leading to exponential drain current suppression consistent with subthreshold MOSFET theory. Experiments on a 64-cell test array confirm the model, revealing position-dependent current attenuation exceeding 40% under high-load conditions. These results directly link device-level physics to array-level performance limits, offering quantitative design guidelines for optimizing interconnect resistance, device parameters, and operating conditions in low-power CIM architectures for embedded artificial intelligence.