Enhanced reliability of ultrathin IZO channel thin-film transistors via p-type Si doping

Abstract

The reliability of indium-zinc-oxide (IZO) channel thin-film transistors (TFTs) was improved by incorporating p-type silicon (p-Si) into the channel layer. Initially, the Mo gate/HfO2 gate dielectric/undoped IZO channel TFT exhibited a threshold voltage (VT) of −3.5 V and a subthreshold swing (SS) of 199 mV/dec. In contrast, doping the IZO channel with p-Si (p-Si:IZO), achieved via co-sputtering with a power of 3 W applied to the p-Si target during deposition, effectively suppressed excess free electron carriers. This modification increased the VT to −2.3 V and improved the SS to 122 mV/dec. X-ray photoelectron spectroscopy analysis revealed an increased O–H bond concentration in the p-Si:IZO channel, suggesting that hydrogen-induced traps, originating from the HfO2 gate dielectric, were passivated. This interpretation is supported by the reduced trap density, estimated at 6.4 × 1013 eV−1 cm−2, extracted from SS measurements. Consequently, the optimized p-Si:IZO channel TFT exhibited robust reliability, with minimal VT shifts of 0.3 and 0.4 V under positive bias stress and positive bias temperature stress at 85 °C, respectively. Furthermore, at cryogenic temperatures (−170 °C), the p-Si:IZO channel TFT achieved a VT of −1.1 V and an SS of 105 mV/dec.