Diameter scaling limit of catalytic silicon nanowires confined by optimized ultrafine sidewall grooves

Abstract

The fabrication of quasi-one-dimensional silicon nanowires (SiNWs) with ultrathin diameters below 10 nm is crucial for enhancing field-effect control in state-of-the-art transistors and is beneficial for building high-performance optoelectronics and biosensors. In this study, we explore the limits of diameter control during the catalytic growth of SiNWs by using an in-plane solid–liquid–solid (IPSLS) mechanism, where SiNWs are guided and confined within narrow sidewall grooves. To achieve tighter growth confinement, a selective etching strategy was developed to produce stable and significantly finer guiding grooves, with heights, depths, and pitches of 15, 16, and 10 nm, respectively. Notably, this innovative groove design enables the production of parallel arrays of ultrathin, monocrystalline-like SiNWs, achieving critical cross-sectional dimensions smaller than 6 nm in one direction or less than 10 nm in both directions. Additionally, we propose a driving-energy-parity model that establishes a lower-bound diameter limit for IPSLS-grown SiNWs at approximately 2.5–4.2 nm. This finding indicates that further dimensional scaling remains feasible by employing even finer sidewall grooves. These results underscore the potential for scaling down ultrathin SiNWs, which is vital for exploring high-performance microelectronics based on a catalytic growth integration strategy.