Demonstration of ferroelectric GaN transistors with area-ratio-controlled AlScN-based MFMIS gate stack

Abstract

In this study, we demonstrate an AlScN/GaN ferroelectric high-electron-mobility transistor (FE-HEMT) employing an area-ratio (AR)-controlled metal–ferroelectric–metal–insulator–semiconductor (MFMIS) gate stack. Configured with an AR of 8:1, the device exhibits a steep subthreshold slope of 26.8 mV/dec and a wide DC memory window of 5.7 V. The FE-HEMT structure facilitates AR tuning to regulate voltage partitioning, effectively preventing dielectric breakdown while enabling extensive polarization switching. Furthermore, a large pulse-induced VTH modulation of 22.9 V is achieved. The device also demonstrates robust endurance up to 3 × 107 cycles with a maintained ΔVTH of ∼7 V, highlighting the potential of the AR-controlled MFMIS FE-HEMT for GaN-based energy-efficient reconfigurable devices.