Co-engineered gate stack for 700 °C thermal budget IGZO transistors with superior bias stability

Abstract

We demonstrate amorphous indium gallium zinc oxide transistors that maintain exceptional bias stress stability even after being subjected to a 700 °C thermal budget, overcoming a critical challenge for monolithic one-transistor-one-capacitor dynamic random access memory (DRAM) integration. This high stability is achieved by a co-engineered gate stack comprising a HfAlO dielectric and an Al2O3 interlayer, referred to as the HfAlO-Al gate stack, which is designed using thermodynamic calculations and ab initio molecular dynamics simulations. The stack combines a high dielectric constant HfAlO dielectric with an elevated crystallization temperature and a flexible, stable Al2O3 interlayer that suppresses atomic interdiffusion, preserving a sharp interface. Experimentally, following a thermal budget of 700 °C for 5 min, the optimized devices exhibit negligible threshold voltage shifts (ΔVth) of only −7 mV under negative bias stress and +17 mV under positive bias stress after 2000 s stress at Vth±4 V. This work provides a viable solution for integrating high-performance oxide semiconductor transistors in advanced DRAM applications.