A sub–10-millisecond neural dynamical system based on phase-change memristors
Abstract
High-fidelity geometry for physical-world modeling demands real-time, dense, and differentiable deformation fields on manifolds. Neural dynamical systems (NDSs) using adaptive stepsize integration with embedded neural networks excel at these tasks but still suffer latency on the order of hundreds of milliseconds. In this work, we report a sub–10-millisecond NDS hardware leveraging the precisely controlled conductance drift of phase-change memristors and their multilevel compute-in-memory capabilities. We fabricated a 40-nanometer NDS chip for the challenging surface reconstruction tasks. Compared with state-of-the-art NDS hardware, our NDS design achieves a latency of 2.12 milliseconds (below 10 milliseconds) for single-iteration NDS computations with an error tolerance of 10 −7 and delivers 3.82× to 36.27× faster speed while consuming 11.75× to 24.73× less power. The end-to-end NDS latency through hardware measurements and simulations outperformed graphics processing unit A100 by 50.38× to 478.18×.
Article Details
Journal Info
Science
American Association for the Advancement of Science
Authors (17)
Lei Cai
New Cornerstone Science Laboratory, Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China.
Yaoyu Tao
New Cornerstone Science Laboratory, Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China.
Chenchen Xie
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China.
Longhao Yan
New Cornerstone Science Laboratory, Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China.
Shiqian Li
Center for Artificial Intelligence Chips, Institute of Artificial Intelligence, Peking University, Beijing, China.
Ruihong Shen
Center for Artificial Intelligence Chips, Institute of Artificial Intelligence, Peking University, Beijing, China.
Zelun Pan
New Cornerstone Science Laboratory, Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China.
Xile Wang
New Cornerstone Science Laboratory, Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China.
Bowen Wang
New Cornerstone Science Laboratory, Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China.
Daijing Shi
New Cornerstone Science Laboratory, Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China.
Yihang Zhu
New Cornerstone Science Laboratory, Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China.
Teng Zhang
Yixin Zhu
Xi Li
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China.
Zhitang Song
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China.
Ru Huang
New Cornerstone Science Laboratory, Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China.
Yuchao Yang
New Cornerstone Science Laboratory, Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China.