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Bayesian-optimized machine learning and experimental study of Al₂O₃-CuO hybrid nanofluid thermal performance in turbulent circular tube flow
Abstract This study explores the thermal behavior of hybrid nanofluids (HNFs) composed of water mixed with equal proportions (50:50) of Al₂O₃ and CuO nanoparticles (NPs) under turbulent flow regimes. The nanofluids (NFs) are prepared in the volume concentrations range of 0–1%. Both experimental investigations and numerical simulations were carried out to evaluate the effects of NP concentration and Reynolds number (Re) on Nusselt number (Nu), friction factor, and entropy generation. Results demonstrated a marked enhancement in heat transfer with increasing NP concentration and flow rate. Notably, the use of HNFs led to a 71% reduction in total entropy generation (TEG) compared to water alone. Empirical correlations were developed to predict the Nu and friction factor accurately. Furthermore, an XGBoost machine learning model was employed to estimate thermal parameters with high precision. The model achieved an R² of 1.000 (training) and 0.991 (testing) with an MSE of 0.001 for TEG. For the friction factor, R² training as 0.686 and R² test as 0.916 (testing) were obtained. Nu model achieved perfect training accuracy (R² = 1.000) and strong testing performance (R² = 0.975, MSE = 29.457). These results affirm the effectiveness of XGBoost in modeling thermofluidic behavior in HNF systems.
Transition-Metal-Free Site-Selective β- and γ-C–H Borylation of Aliphatic Amines
A 1.2-V 7.76-ENOB 1-MS/s single-ended SAR ADC in 65-nm CMOS for biomedical applications
Abstract A successive approximation register analog-to-digital converter (SAR ADC) is a promising approach used in biomedical applications due to its energy-efficiency architecture with less complex hardware implementation. The core building blocks of SAR ADC are sample-and-hold switch (S/H), comparator, logic control register, and digital-to-analog converter (DAC). To enhance the overall performance, a high-isolation CMOS bootstrap S/H switch has been used. The SFDR of proposed ADC has increased by up to 2.2 dB. Also, we propose a double-tail single-ended dynamic latch comparator with extra pair PMOS transistors that save power by up to 7.5% as compared to the traditional double-tail dynamic comparator. Moreover, after adding these pair of transistors into conventional double tail dynamic comparator without any calibration cost, the SNDR has increased by more than 2 dB and 0.3bit improvement of ENOB. Furthermore, a synchronous modified SAR logic control register based on low-power D flip-flops (FFs) is proposed. A metal-isolator-metal capacitor (MIM) with a modified capacitance reduction configuration is used to improve the active area of the capacitive DAC (CDAC) compared to the conventional CDAC with 36.7% saving power. The proposed ADC has been implemented using a 65-nm TSMC CMOS process, 1.2 V supply voltage with a sampling rate of 1 MS/s. An active area of 0.00585 mm 2 with a total post-result power consumption of 5.75 µW has been accomplished for the proposed fully integrated ADC.