Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field

Md Rownak Hossain; Md Sazedur Rahman; Kh Shahriya Zaman; Walid El Fezzani; Mohammad Arif Sobhan Bhuiyan; Chia Chao Kang; Teh Jia Yew; Mahdi H. Miraz

doi:10.1038/s41598-025-99100-x

Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field

M Md Rownak Hossain M Md Sazedur Rahman K Kh Shahriya Zaman W Walid El Fezzani M Mohammad Arif Sobhan Bhuiyan C Chia Chao Kang T Teh Jia Yew M Mahdi H. Miraz

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Article Details

Journal Scientific Reports

Volume / Issue Vol. 15, Issue 1

Published April 29, 2025

DOI 10.1038/s41598-025-99100-x

ISSN 2045-2322

Publisher Nature Portfolio

Journal Info

Scientific Reports

Nature Portfolio

ISSN: 2045-2322 Open Access Life Sciences

Authors (8)

M

Md Rownak Hossain

M

Md Sazedur Rahman

K

Kh Shahriya Zaman

W

Walid El Fezzani

M

Mohammad Arif Sobhan Bhuiyan

C

Chia Chao Kang

T

Teh Jia Yew

M

Mahdi H. Miraz

Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field

Article Details

Journal Info

Authors (8)

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