Design of a low-delay 4-bit parallel prefix adder using QCA technology

Abstract

Abstract This paper presents a novel low-delay 4-bit Parallel Prefix Adder (PPA) implemented as a multilayer circuit using Quantum Dot Cellular Automata (QCA) technology. PPAs are among the most suitable architectures for high-speed digital design, offering significant advantages in scalability and performance over traditional Ripple Carry Adders (RCAs) and Carry Flow Adders (CFAs). The proposed design provides a fast, compact, ergonomic, and energy-efficient alternative to QCA adders adopting these architectures. This work enhances existing PPA modules, including XOR gates, Half Adders, Black Modules, and Gray Modules, by tailoring them to optimally fit the core PPA structure. The proposed PPA achieves a 26% reduction in cell count, a 31% reduction in area and a 57% reduction in delay compared to existing PPA designs. Utilizing a hybrid crossover methodology, the design reduces delay by 25% relative to the fastest 4-bit QCA adder reported in the literature and lowers the area-delay cost by 11% compared to the most economical design. Simulated using the QCADesigner-E Version 2.2 software, the proposed adder demonstrates energy dissipation comparable to existing designs, solidifying its practicality and efficiency for high-speed QCA-based applications.