Vertical Self‐Rectifying Memristive Arrays for Page‐Wise Parallel Logic and Arithmetic Processing

Abstract

Abstract Logic‐in‐memory (LIM) architectures are explored to address the data transfer bottleneck of conventional von Neumann architectures by integrating computation directly within memory arrays. Among various candidates, memristor‐based LIM systems have gained significant attention due to their non‐volatile switching behavior and compatibility with dense integration. In this work, a page‐wise LIM architecture is implemented using a 3D vertical resistive random‐access memory array composed of self‐rectifying Pt–Ta 2 O 5 –Al:HfO 2 –TiN memristors. Two logic primitives—1 M and 2 M logic—are employed to perform intra‐page and inter‐page operations, respectively, enabling core Boolean functions to be executed entirely within the array through resistive state transitions. Based on these logic operations, a memristive arithmetic logic unit (mALU) is designed to perform essential arithmetic functions, including addition, subtraction, increment, and decrement. Owing to the vertical structure of vertical resistive random‐access memory, a 2‐bit full adder is implemented with a footprint of only three cells and completed in 12 steps. The proposed intra‐and inter‐page operations, along with complete mALU functionality, are experimentally demonstrated with high reproducibility. Combined with significantly reduced spatiotemporal cost, these results highlight the promise of this architecture for scalable and energy‐efficient in‐memory computing.