Thermal performance enhancement of complementary field-effect transistors via comparative analysis of power delivery structures

Abstract

Self-heating effects are a growing reliability challenge in vertically stacked Complementary Field-Effect Transistors (C-FETs) due to structural thermal isolation introduced by vertical integration—unlike in conventional lateral CMOS. To address this, we investigate Buried Power Rail (BPR) architecture in the Middle-of-Line (MOL) region, replacing conventional front-side power delivery networks (FS-PDNs) to enhance vertical thermal conduction in nanoscale (∼3 nm node) C-FETs. 3D electro-thermal technology computer-aided design (TCAD) simulations were conducted using a comprehensive thermal model that incorporates size-dependent conductivity, interfacial thermal resistance, and package-aware boundary conditions. The BPR configuration reduced peak lattice temperature by up to 3.7% and thermal resistance by 7.5% compared to FS-PDN while maintaining electrical performance even under middle dielectric isolation variation. An electro-thermal figure-of-merit, combining delay and temperature rise, improved by 3.1% despite modest resistance–capacitance delay trade-offs, demonstrating superior thermal robustness. These results provide practical design insights for enabling reliable nanoscale C-FET operation through MOL-level thermal path engineering.