The impact of interface traps on the subthreshold characteristics of III–V vertical nanowire tunnel field-effect transistors

Abstract

In this work, in an effort to study tunneling physics, we have performed extensive electrical characterization of two generations of top-down III–V vertical nanowire tunnel field-effect transistors (TFETs). The widely different MOS interface trap densities of two generations of TFETs and the availability of metal–oxide–semiconductor field-effect transistors fabricated simultaneously enable direct study of various effects of interface states on TFETs. Interface trap-assisted tunneling was suppressed in the second generation TFETs, and the residual temperature dependence of the second generation TFETs can be explained by a band-edge sharpness of 120 mV/dec.