Role of Si/dielectric interface traps on the reliability of tree-shaped complementary FETs for sub-3 nm technology nodes

Abstract

Abstract Complementary (C) FETs enable superior scaling and electrostatics for sub-3 nm nodes but the increased Si/dielectric interface reliability a critical concern, and its impact on Tree-shaped CFETs is investigated for the first time in this work. The Si/dielectric interface trap density (N it ) is varied from 1 to 9 × 10 12 cm − 2 for both acceptor and donor traps to evaluate their influence on digital, analog, RF, and circuit characteristics. With increasing N it , in the n-type (p-type) device, acceptor (donor) traps repel electrons (holes), reducing I ON while suppressing I OFF by ~ 5 orders, improving the I ON /I OFF ratio. In p-type (n-type) device acceptor (donor) traps attract holes (electrons), increasing I ON by ~ 68% (~ 58%) but reducing the ratio to 10 2 due to higher leakages. Notably, when the N it exceeds 4 × 10 12 cm − 2 , the switching ratio deteriorates below 10 4 for donor (acceptor) traps in the n-type (p-type) device due to pronounced trap-assisted leakage. The findings demonstrate that the Tree-shaped CFET maintains strong electrostatic integrity till ≤ 4 × 10 12 cm − 2 and stable analog/RF behavior even under severe Si/dielectric interface trap perturbations. The Tree-CFET CMOS inverter shows robust circuit behavior with ~ 2.9 ps delay at moderate trap densities, highlighting the need for precise interface engineering for sub-3 nm nodes.