Predictive modeling of Z-shaped gate source pocket TFET using machine learning and TCAD simulation data

Abstract

Abstract Tunnel field-effect transistors (TFETs) are considered to be promising devices for ultra-low-power and energy-efficient applications because of their steep subthreshold swing and low leakage current. In this work, a Z-shaped Gate source pocket TFET (ZSP-TFET) is designed and modeled using an ML-assisted modeling framework for efficiently predicting its electrical performance. This device features a source based on SiGe material, a silicon channel and a Z-shaped dual-gate architecture aimed at augmenting band-to-band tunneling and improving the electrostatic control. Extensive TCAD simulations have been performed to provide a complete dataset by changing critical device parameters: Oxide thickness ( t ox ), Source pocket thickness ( t sp ), Gate Work function (WF), Channel length ( L ch ) and V GS . Corresponding output parameters are the I D and SS used to train and validate several ML regression models. Among the considered algorithms, the Random Forest Regressor (RFR) achieves much higher prediction accuracy due to its strong capability to model the nonlinear behaviour of ZSP-TFET. This proposed ML model yields a maximum R 2 score of up to 99.41% with a minimum RMSE of 0.011 for the 90–10 split in training and testing datasets, respectively, which confirms excellent agreement between the simulated and predicted results. The parameter-wise validation of I ON , I OFF , and SS with regard to L ch , t ox , t sp , and WF variations returns an R 2 value above 0.99 for each case, which further establishes the robustness and reliability of the model performance. Moreover, comparative analysis among other ML algorithms establishes the efficacy of the applied RFR approach in predicting more accurate TFET performance. In this respect, the accomplished ML-assisted approach could reduce the computational cost significantly without sacrificing the accuracy of prediction. Therefore, this will be a strong tool for optimization and fast analyzing advanced TFET architectures such as ZSP-TFET.