Novel approximate adaptive carry lookahead adder for error resilient applications with generic method for error analysis

Abstract

Abstract The paper presents a novel architecture of approximate adder and a novel generic error analysis method. The proposed architecture judiciously make use of time axis based parallelism of components to improve delay and simultaneously improvement in error parameters due to adaptive increase in group-size of carry generating blocks. The synthesis of architectures for same bit length has shown area, power, and delay improvement by 4.91%, 5.59%, 14.92% respectively with respect to state of the art architectures based on truncation of carry chain when synthesized under same constraints and same operating conditions. In comparison to ETA-I, ETA-II and GeAr, proposed method has shown improvement in delay by 9%, 17.9% and 21.3% respectively. Error analysis is done for proposed adder using random probabilistic method and generic analysis method. The generic error analysis method has shown error parameter results are in close agreement with values found with application of binary random numbers, with very large sample size, for all adder architectures with different size, group-size and window-size. Generic analysis method and random probabilistic method based error rate calculation varies by the least, with a value of 0.49% and a maximum of 13.85%.