Microstructure Optimization via Grain‐Boundary Segregation to Enhance DC Bias Dielectric Performance of BaTiO
                    <sub>3</sub>
                    Multilayer Ceramic Capacitors (Adv. Mater. 1/2026)

Ji‐Sang An; Juneseo Ahn; Younghwan Lim; Hyung Bin Bae; Jungho Ryu; Sung‐Yoon Chung

doi:10.1002/adma.71873

Microstructure Optimization via Grain‐Boundary Segregation to Enhance DC Bias Dielectric Performance of BaTiO <sub>3</sub> Multilayer Ceramic Capacitors (Adv. Mater. 1/2026)

J Ji‐Sang An (Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology Daejeon 34141 South Korea) J Juneseo Ahn Y Younghwan Lim (Department of Materials Science and Engineering) H Hyung Bin Bae (KAIST Analysis Center) J Jungho Ryu S Sung‐Yoon Chung (Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology Daejeon South Korea)

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Article Details

Journal Advanced Materials

Volume / Issue Vol. 38, Issue 1

Published January 01, 2026

DOI 10.1002/adma.71873

ISSN 0935-9648

Publisher Unknown Publisher

Journal Info

Advanced Materials

Unknown Publisher

ISSN: 0935-9648 Physical Sciences

Authors (6)

J

Ji‐Sang An

Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology Daejeon 34141 South Korea

J

Juneseo Ahn

Y

Younghwan Lim

Department of Materials Science and Engineering

H

Hyung Bin Bae

KAIST Analysis Center

J

Jungho Ryu

S

Sung‐Yoon Chung

Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology Daejeon South Korea

Microstructure Optimization via Grain‐Boundary Segregation to Enhance DC Bias Dielectric Performance of BaTiO <sub>3</sub> Multilayer Ceramic Capacitors (Adv. Mater. 1/2026)

Article Details

Journal Info

Authors (6)

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