Impact of geometric parameters on the electrical performances of pseudo-vertical GaN-on-Si p–n diodes with avalanche capability via selective epitaxy

Abstract

In this study, we present a GaN-on-Si pseudo-vertical p–n diode fabricated using selective area growth (SAG). The device achieved a high current density of 1.5 kA cm−2 and a low specific on-resistance (Ron,sp) of 3.3 mΩ cm2. A very high on/off current ratio (Ion/Ioff) of 1012 was also recorded. Notably, for the first-time using SAG, uniform avalanche breakdown behavior of 850 V was demonstrated through temperature-dependent reverse bias measurements, corresponding to a Baliga figure of merit of 0.2 GW cm−2. These results emphasize the advantages of localized epitaxy in achieving high-quality p–n junctions on Si substrates, paving the way for scalable, high-performance GaN power devices monolithically integrated with Si technology. To evaluate the influence of geometric parameters on epitaxial quality and device performance, the mesa spacing was systematically varied while keeping the diameter fixed. Optimal results were obtained with 5–15 μm spacing, offering the best trade-off between forward conduction efficiency and reverse blocking robustness. This comprehensive investigation underscores the importance of geometric optimization and localized epitaxy in advancing high-performance GaN-on-Si p–n diodes for next-generation power applications.