High‐Performance Air‐Stable Polymer Monolayer Transistors for Monolithic 3D CMOS logics

Abstract

Abstract The monolayer transistor, where the semiconductor layer is a single molecular layer, offers an ideal platform for exploring transport mechanisms both theoretically and experimentally by eliminating the influence of spatially correlated microstructure. However, the structure‐property relations in polymer monolayers remain poorly understood, leading to low transistor performance to date. Herein, a self‐confinement effect is demonstrated in the polymer monolayer with nanofibrillar microstructures and edge‐on orientation, as characterized by the 4D scanning confocal electron diffraction method. The polymer chains align parallel to the nanofiber long axis, while the π‐stacking direction aligns perpendicular to this axis. To reduce the trap density at the semiconductor/dielectric interface, a top‐gate configuration is employed with CYTOP as gate dielectric, and the resulting monolayer transistors achieve a field‐effect mobility of 7.12 cm 2 V −1 s −1 , an on/off ratio of 10⁸, and a subthreshold swing of 0.21 V dec −1 , among the performance records for polymer monolayer transistors. Notably, the top‐gate architecture allows self‐encapsulation, and the monolayer network induces the morphologic lock effect, contributing to a remarkable device stability over 1260 days. Additionally, the low thermal budget of this polymer monolayer transistor enables the monolithic 3D integration with n‐type oxide transistor, resulting in hybrid complementary inverters with reasonable voltage amplification capabilities.