From Planar to 3D: The Evolution of Complementary Field‐Effect Transistor for Next‐Generation Semiconductor Nodes

Abstract

ABSTRACT Complementary Field‐Effect Transistor (CFET) technology is emerging as a critical point to extending Moore's Law by transitioning device scaling and integration from 2‐ to 3D architectures. Recent advancements, including silicon‐based homogeneous CFETs and van der Waals‐based heterogeneous CFETs, have demonstrated significant progress, yet a comprehensive and up‐to‐date review is absent to further advance the field. This work explores CFET fabrication methodologies, comparing the advantages and challenges of Monolithic and Sequential integration approaches, with a focus on thermal management, process complexity, and material compatibility. We highlight the critical role of layered van der Waals materials in addressing thermal constraints and enhancing gate control, leveraging their atomic‐scale thickness and unique electronic properties. Furthermore, we discuss strategies to overcome key challenges such as achieving balanced electrical characteristics, optimizing thermal management, and minimizing parasitic capacitance through innovative channel engineering, gate‐dielectric design, and structural optimization. The co‐design principles of CFET architectures are also examined, showcasing their potential in logic circuits, memory units, and computing‐in‐memory systems. This review provides a forward‐looking perspective on CFET technology, emphasizing the need for continued innovation in material‐processing‐structure co‐design and co‐optimization to unlock new frontiers in semiconductor technology.