Ferroelectric nanosheet FET with surrounded gate for mitigating dead zone and implementing reconfigurable logic-in-memory circuit

Abstract

Although a nanosheet ferroelectric field-effect transistor (FeNSFET) with the gate-all-around structure has proved to be a promising solution to enhance memory density, device performances could be greatly affected by the corner dead zone of ferroelectric polarization. In this study, a novel FeNSFET with a surrounded gate (S-FeNSFET), which is different from that with the conventional all-around gate (A-FeNSFET), was proposed to alleviate the dead zone issue. Through Technology Computer Aided Design simulation, in the case of two nanosheets (NSs), the memory window (MW) of the S-FeNSFET is ∼85% larger than that of the A-FeNSFET. By analyzing the ferroelectric polarization distribution, it is confirmed that the corner dead zone could be effectively mitigated to improve ferroelectric polarization in the S-FeNSFET, thereby enhancing memory performances. Further comparison between these two devices with different NS numbers reveals that the MW and subthreshold swing (SS) of the A-FeNSFET almost do not change with the NS number, whereas the MW of the S-FeNSFET increases as the NS number increases, together with a slightly degraded SS. Based on this S-FeNSFET configuration, a complementary reconfigurable logic-in-memory circuit was further designed and validated. The dynamic reconfiguration among AND, OR, and XOR logic functions was successfully achieved by using N-type and P-type S-FeNSFETs in the case of three NSs. This work provides important guidance for advancing the development of FeNSFET technology in the next-generation memory and logic applications.