Energy-efficient integer-only vs. floating-point FLBMF filters for low-power embedded image denoising

Abstract

Abstract Fuzzy logic-based median filters (FLBMF) are widely applied in medical imaging to suppress impulse noise while preserving diagnostically relevant structures. Floating-point implementations, although precise, impose substantial computational and memory demands, limiting their deployment on embedded, portable, or low-power imaging systems. This study presents a systematic evaluation of integer-only FLBM and floating-point FLBMF implementations, analyzing trade-offs between denoising performance, computational cost, and hardware efficiency. The integer-only FLBM design leverages quantized membership functions, fixed-point arithmetic, and optimized rule evaluation to reduce arithmetic complexity while maintaining perceptual fidelity, with the floating-point version serving as a precision benchmark. Evaluations were conducted on noisy mammography datasets across multiple noise densities (ρ = 0.3–0.7) using an ARM Cortex-M7 microcontroller and a Xilinx Zynq-7020 FPGA. Performance metrics include image quality (PSNR, SSIM, VIF, FOM), computational efficiency, memory usage, energy consumption, and hardware resource utilization. Experimental results indicate that integer-only FLBMF reduces memory usage by up to 40% and execution time by up to 55% on embedded processors, while maintaining perceptually equivalent denoising quality (ΔPSNR ≤ 0.5dB, ΔSSIM ≤ 0.01). On FPGA platforms, integer-only FLBM implementations achieve lower DSP and LUT utilization, reduced power consumption, and higher operating frequency compared to floating-point versions. Comparisons with classical median, adaptive median, and TV-based filters show that both integer-only FLBM and floating-point FLBMF substantially outperform these baselines. These findings establish integer-only FLBMF as a hardware-friendly, energy-efficient, and clinically faithful solution for real-time, low-power medical imaging, representing the first systematic evaluation of such implementations across MCU and FPGA platforms.