Controlled trap formation in SiC metal–oxide–semiconductor structures via gate bias stress and its impact on the performance of metal–oxide–semiconductor field-effect transistors

Abstract

We regulated trap formation in silicon carbide (SiC) metal–oxide–semiconductor (MOS) structures by applying gate bias stress and evaluated how traps at different energy levels degrade the performance of SiC MOS field-effect transistors. Specifically, samples with systematically varied nitridation conditions were prepared, and the impact of interface traps generated under negative-bias stress at an elevated temperature of 300 °C was investigated. Carrier trapping behavior and mobility degradation trends were examined using the transfer characteristics together with Hall-effect measurements. In samples without nitridation, the interface states in the shallow-energy region (EC − ET = 0–0.10 eV) increased under stress, and they were found to act as carrier traps. In nitrided samples, the interface states in relatively deep energy regions (EC − ET = 0.15–0.35 eV) increased and functioned as Coulomb-scattering centers, thereby reducing the free electron mobility.