Chip‐Scale Graphene/IGZO Cold Source FET Array Enabling Sub‐60 mV dec <sup>−1</sup> Super‐Steep Subthreshold Swing

S Seyoung Oh (Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea) O Ojun Kwon (Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea) J Jongwon Yoon E Eunjeong Cho M Min Jeong Kim W Wondeok Seo (Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea) M MinHee Kim S Shinhoi Kim (Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea) Y Yeongeun Kwon (Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea) Y Yung Joon Jung (Department of Mechanical and Industrial Engineering Northeastern University Boston MA 02115 USA) K Kyungrok Kang (DRAM Yield Enhancement Team Samsung Electronics 1‐1, Samsungjeonja‐ro Hwasung‐City Gyeonggi‐do 18448 Republic of Korea) W Woojin Park Y Yonghun Kim B Byungjin Cho (Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea)

Abstract

Abstract In this study, the first sub‐60 mV dec −1 super‐steep subthreshold swing (SS) of graphene/InGaZnO (IGZO) cold‐source field‐effect transistor (CSFET) arrays is demonstrated. The linear density of states of the Dirac‐cone‐type graphene suppresses the Boltzmann thermal tail near the graphene/IGZO interface which in turn causes super‐exponentially decaying electron density with increasing energy, leading to an extremely low off current and SS value. In particular, by introducing an HfO 2 high‐k dielectric with a low body factor, the surface potential is effectively modulated, further reducing SS by ≈46.4 mV dec −1 . Furthermore, highly uniform sub‐60 mV dec −1 SS with a yield of ≈89.1% is achieved in the IGZO CSFET 8 × 8 array devices, with a record SS value of 23.66 mV dec −1 compared to previously reported oxide‐semiconductor transistors. The proposed IGZO CSFET device is expected to drive significant advancements in high‐speed and ultralow‐power electronic circuits.

Article Details

Volume / Issue Vol. 38, Issue 7
Published February 01, 2026
ISSN 0935-9648
Publisher Unknown Publisher

Journal Info

Advanced Materials

Unknown Publisher

ISSN: 0935-9648 Physical Sciences

Authors (14)

S

Seyoung Oh

Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea

O

Ojun Kwon

Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea

J

Jongwon Yoon

E

Eunjeong Cho

M

Min Jeong Kim

W

Wondeok Seo

Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea

M

MinHee Kim

S

Shinhoi Kim

Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea

Y

Yeongeun Kwon

Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea

Y

Yung Joon Jung

Department of Mechanical and Industrial Engineering Northeastern University Boston MA 02115 USA

K

Kyungrok Kang

DRAM Yield Enhancement Team Samsung Electronics 1‐1, Samsungjeonja‐ro Hwasung‐City Gyeonggi‐do 18448 Republic of Korea

W

Woojin Park

Y

Yonghun Kim

B

Byungjin Cho

Department of Advanced Materials Engineering Chungbuk National University Chungdae‐ro 1, Seowon‐Gu Cheongju Chungbuk 28644 Republic of Korea