Artificial Optoelectronic Synapse Featuring Bidirectional Post‐Synaptic Current for Compact and Energy‐Efficient Neural Hardware
Abstract
Abstract Conventional hardware neural networks (HW‐NNs) have relied on unidirectional current flow of artificial synapses, necessitating a differential pair of the synapses for weight core implementation. Here, an artificial optoelectronic synapse capable of bidirectional post‐synaptic current ( I PSC ) is presented, eliminating the need for differential synapse pairs. This is achieved through an asymmetric metal contact structure that induces a built‐in electric field for directional flow of photogenerated carriers, and a charge trapping/de‐trapping layer in the gate stack ( h ‐BN/weight control layer) that can modulate the surface potential of the semiconductor channel (WSe 2 ) using electrical signals. This structure enables precise control over the direction and magnitude of injected charge. The device demonstrates key synaptic behaviors, such as long‐term potentiation/depression and spike‐timing‐dependent plasticity. A fabricated 3 × 2 artificial synapse array shows that the bidirectional I PSC characteristic is compatible with multiply‐accumulate operations. Finally, the feasibility of these synapses in HW‐NNs is demonstrated through training and inference simulations using the MNIST handwritten digits dataset, yielding competitive recognition rates and reduced total energy consumption for updating weights of the weight core compared to unidirectional I PSC ‐based systems. This approach paves the way toward more compact and energy‐efficient brain‐inspired computing systems.
Article Details
Authors (24)
Hogeun Ahn
Department of Electrical and Computer Engineering Sungkyunkwan University Suwon 16419 Republic of Korea
Yena Kim
Department of Semiconductor Convergence Engineering Sungkyunkwan University Suwon 16419 Republic of Korea
Seunghwan Seo
Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak‐ro, Yuseong‐gu Daejeon 34141 Republic of Korea
Junseo Lee
Sehee Lee
Department of Electrical and Computer Engineering Sungkyunkwan University Suwon 16419 Republic of Korea
Saeyoung Oh
Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology Daejeon 34141 Republic of Korea
Byeongchan Kim
Department of Brain Sciences, Daegu Gyeongbuk Institute of Science and Technology
Jeongwon Park
Sumin Kang
Yuseok Kim
Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology Daejeon 34141 Republic of Korea
Ayoung Ham
Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak‐ro, Yuseong‐gu Daejeon 34141 Republic of Korea
Jaehyun Lee
Donggeon Park
Graduate School of Semiconductor Technology Korea Advanced Institute of Science and Technology Daejeon 34141 Republic of Korea
Seongdae Kwon
Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak‐ro, Yuseong‐gu Daejeon 34141 Republic of Korea
Doyoon Lee
Department of Mechanical Engineering Massachusetts Institute of Technology Cambridge MA 02138 USA
Jung‐El Ryu
Department of Mechanical Engineering Massachusetts Institute of Technology Cambridge MA 02138 USA
June‐Chul Shin
Department of Mechanical Engineering Massachusetts Institute of Technology Cambridge MA 02138 USA
Atharva Sahasrabudhe
Ki Seok Kim
Department of Mechanical Engineering Massachusetts Institute of Technology Cambridge MA 02138 USA
Sang‐Hoon Bae
Department of Mechanical Engineering and Materials Science Washington University in St. Louis St. Louis Missouri 63130 USA
Kibum Kang
Graduate School of Semiconductor Technology Korea Advanced Institute of Science and Technology (KAIST) Daejeon Republic of Korea
Jeehwan Kim
Saeroonter Oh
Jin‐Hong Park
Department of Electrical and Computer Engineering Sungkyunkwan University Suwon 16419 Republic of Korea