Architecture of 3D magnetic domain wall memory for suppressing bit-shift error

P Pham Nam Hai (Department of Electrical and Electronic Engineering, Institute of Science Tokyo 1 , Tokyo 152-8550,) T Takanori Shirokura (Department of Electrical and Electronic Engineering, Institute of Science Tokyo 1 , 2-12-1 Ookayama, Meguro City, Tokyo 152-8552,) N Nguyen Huynh Duy Khang (Department of Physics, Ho Chi Minh City University of Education 3 , 280 An Duong Vuong Street, District 5, Ho Chi Minh City 738242,)

Abstract

We propose an architecture for the suppression of magnetic domain wall shift error in 3D magnetic domain wall memory, which utilizes the spatially modulated perpendicular magnetic anisotropy (PMA) of magnetic layers that are deposited on the side walls of multilayers of different oxide materials. We experimentally identified the oxide material candidates for such implementation and found that CrOx can generate the largest PMA while GdOx generates the smallest PMA of Pt/Co/Pt multilayers. Our proposed architecture can be a key to realizing 3D magnetic domain wall racetrack memory with low bit-shift error.

Article Details

Volume / Issue Vol. 138, Issue 23
Published December 21, 2025
ISSN 0021-8979
Publisher American Institute of Physics

Journal Info

Journal of Applied Physics

American Institute of Physics

ISSN: 0021-8979 Physical Sciences

Authors (3)

P

Pham Nam Hai

Department of Electrical and Electronic Engineering, Institute of Science Tokyo 1 , Tokyo 152-8550,

T

Takanori Shirokura

Department of Electrical and Electronic Engineering, Institute of Science Tokyo 1 , 2-12-1 Ookayama, Meguro City, Tokyo 152-8552,

N

Nguyen Huynh Duy Khang

Department of Physics, Ho Chi Minh City University of Education 3 , 280 An Duong Vuong Street, District 5, Ho Chi Minh City 738242,