An efficient serialized hardware implementation of the ASCON algorithm

Abstract

Abstract The era of the Internet of Things (IoT) introduces new technologies alongside challenges in hardware and data transfer security. This work presents the hardware implementation of the Lightweight Cryptography (LWC) algorithm ASCON-128, specifically targeting IoT applications and edge devices with stringent power and area constraints. The proposed design utilizes a serialized hardware architecture that minimizes logic usage, resulting in a compact area and low power consumption. It maintains adequate throughput through a sponge-based construction in authenticated mode. On FPGA, the design operates on the ultra-low-power platform, Lattice iCE40, achieving maximum frequency (Fmax) of 228.8 MHz with only 582 Lookup Tables (LUTs), 418 flip-flops, and 2.28 mW at 13.7 MHz. The Application-Specific Integrated Circuit (ASIC) implementation using 16 nm TSMC FinFET technology achieves a power consumption of 0.254 mW and an area of 1.341 kilo gate-equivalents (kGE), delivering an energy efficiency of 0.106 nJ/bit and a throughput of 2.381 Mbps at 100 MHz. These results highlight the effectiveness of the proposed ASCON-128 architecture for secure, low-power IoT and RFID applications.